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Memory Timings Explained

Now days it seems like everybody is tweaking their systems to get every last bit of performance out of them. Something that is often overlooked that plays a significant rold in your systems performance is memory bandwidth. This is a very tricky thing, sometimes a lower bus speed with faster timings is considerably better than just increasing your bus speed. When you are shopping for RAM you don't want to buy just cas 2 RAM. It is possible that you can get 2/3/3 RAM. You want to make sure you get good stuff. All 3 of these timings will greatly affect your system performance. You'll want to make sure you get 2/2/2 RAM what do these 3 numbers mean?

The first number is the CAS latency. The second number is the TRCD. The last number is the TRP. What on earth are these things and why do they affect my performance so much? That's exactly why I've written this article. Here we will try and explain to you what these different settings you see all the time do and try to help you have a better understanding of why these make your system go so much faster.

Cas Latency

CAS means Column Address Strobe. The Webster's Dictionary defines latency as "the interval between stimulus and response" just in case that word isn't familiar to you.

This controls the timing delay (in clock cycles) before the RAM starts a read command after receiving it. Settings are usually 2 or 2.5 This setting has more affect on system performance than any other RAM setting. Since this is the number of cycles the CAS needs to find the correct address of the data that it is looking for. That is why your entire system runs quite a bit faster when the data can be fetched in 2 cycles rather than 2.5.

I'll pull a quote from a guide from Corsair who BTW makes the XMS line of memory that I certainly approve of for high speeds and good timings.

"To understand this let's walk through a simplified version of how the memory controller actually reads the memory. First, the chip set accesses the ROW of the memory matrix by putting an address on the memory's address pins and activating the RAS signal. Then, we have to wait a few clock cycles (known as RAS-to-CAS Delay). Then, the column address is put on the address pins, and the CAS signal is activated, to access the correct COLUMN of the memory matrix. Then, we wait a few clock cycles -- THIS IS KNOWN AS CAS LATENCY! -- and then the data appears on the pins of the RAM."

RAS to CAS Delay (TRCD) This field allows you to set the number of cycles for a timing delay between the CAS and RAS strobe signals, used when DRAM is written to, read from or refreshed. Lower settings result in faster performance. 3T, 2TBank Interleave

TRP  indicates how fast SDRAM can terminate one row access and starts another one.

TRAS The TRAS timing can be typically be set to 5, 6, and 7. TRAS is a timing that has little effect on performance, but has a huge effect on the maximum stable speed your RAM can run. We recommend always using the slowest ( highest number ) TRAS setting available; usually on AMD motherboards this would be 6 or on P4 boards this would be 7.

Row Precharge Time
This item controls the number of cycles for Row Address Strobe (RAS) to be allowed to precharge. If Insufficient time is allowed for the RAS to accumulate its charge before DRAM refresh, refresh may be incomplete and DRAM may fail to retain data.  2T or 3T

RAS Pulse Width This setting allows you to select the number of clock cycles allotted for the RAS pulse width, according to DRAM specs. The lower this is set the faster RAM performance. 6T,5T

Bank Interleave This files selects 2-bank or 4-bank interleave for the installed RAM. Disabled, 2-way and 4-way.

Basically, a bank activate command can open one bank at the time and then the readout will occur after tRCD and CAS-DL. However, simultaneously, the memory controller can issue another bank activate command in the cycle after the first command was issued and, thus open the next bank. If the controller knows that the next set of data is going to be in a different bank, it can issue read commands to the next location without trashing the first bank's data burst.

Burst length This is a technique that DRAM uses to predict the address of the next memory location to be accessed after the first address is accessed. 4QW, 8QW

Command Rate This is the setting that selects the speed of the SDRAM signal controller. If set to 1T the memory controller is running in synchronization with your bus speed. 1T will increase your memory bandwidth but a LOT of memory brands will really have trouble running this at decent speeds. This setting will have to be played with a LOT while your increasing your FSB speed. It does in fact increase your memory bandwidth but will often lower your max bus speed so much that it just isn't worth using.

ECC "ECC" stands for "Error Checking and Correction". When ECC is enabled in the BIOS the memory check will take considerably longer than it does with normal RAM. you will just have to be patient. It does not show any special messages or any info telling you why it is taking so long. ECC RAM is more expensive. On a stick of RAM that has 8 modules a ninth will need to be added for error checking. on a 16 module stick 2 more modules will be added. The added modules are what increase the price. This will hinder your performance slightly and isn't needed by us. It's geared more towards the server market.This feature is similiar to parity back in the old days. Most of the BSOD's we always saw in the win9x days get healed by having ECC memory. Commonly RAM will have an error about once a month if it is being run 24 hours a day.

Registered The Athlon64 boards out right now require registered memory. What is this? Registered memory is slightly different than ECC memory. Most registered memory HAS ECC but to be a registered DIMM doesn't always mean that it has ECC. The registered part of the memory acts like a buffer it basically guides the data to the appropriate place. It was designed to give assistance when massive amounts of data are being transferred. Common in high end workstations and servers. If you're going this high end you better make sure the memory has ECC too.

SDRAM PH limit  Page hit limit.

Up to 60% of all read requests fall within the same page which is called a page hit. Setting the page hit limit limits the number of times this data can be read from before the data is refreshed. Refreshing the data more often will cause a small performance hit while refreshing not often enough can and will cause stability problems depending on the quality of your RAM. Over time capacitors lost their charge. If the data is not refreshed often enough data in the memory can very well be lost which most of the time will lead to a lockup.

SDRAM idle cycle limit Setting this will determine how frequently idle banks will be refreshed. Even if a bank is empty it will still be refreshed. Generally the available settings are from 0 to 8 cycles.

In Closing.

I'm currently experimenting with some RAM to try and give you a good idea of how these various settings affect your systems performance. If you have any other timings on your board that you'd like more information on please post in this thread and I'll try to get this article updated with any other timings you want to know about.